HD64F2638F20J Datasheet, PDF (723/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 16 Controller Area Network (HCAN)
16.3.6 HCAN Halt Mode
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 16-12 shows a flowchart of the HCAN halt mode.
MCR1 = 1
Bus idle?
No
Yes
MBCR setting
MCR1 = 0
CAN bus communication possible
: Settings by user
: Processing by hardware
Figure 16-12 HCAN Halt Mode Flowchart
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). However, if the CAN bus is operating at the time of a transition, the transition to
HCAN ALT mode is delayed until the bus becomes idle.
HCAN halt mode is cleared by clearing MCR1 to 0.
16.3.7 Interrupt Interface
There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned.
Table 16-5 lists the HCAN interrupt sources.
With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is
implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register
(IMR).
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 673 of 1458