HD64F2638F20J Datasheet, PDF (656/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
• Notes on ICDR Reads and ICCR Access in Slave Transmit Mode
In a transmit operation in the slave mode of the I²C bus interface, do not read the ICDR
register or read or write to the ICCR register during the period indicated by the shaded portion
in figure 15-25.
Normally, when interrupt processing is triggered in synchronization with the rising edge of the
9th clock cycle, the period in question has already elapsed when the transition to interrupt
processing takes place, so there is no problem with reading the ICDR register or reading or
writing to the ICCR register.
To ensure that the interrupt processing is performed properly, one of the following two
conditions should be applied.
(1) Make sure that reading received data from the ICDR register, or reading or writing to the
ICCR register, is completed before the next slave address receive operation starts.
(2) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0
is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in
order to involve the problem period in question before reading from the ICDR register, or
reading or writing to the ICCR register.
Waveforms if
problem occurs
SDA
SCL
TRS
R/W
8
Address received
A
9
Period when ICDR reads and ICCR
reads and writes are prohibited
(6 system clock cycles)
Bit 7
Data transmission
ICDR write
Detection of 9th clock
cycle rising edge
Figure 15-25 ICDR Read and ICCR Access Timing in Slave Transmit Mode
Page 606 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010