HD64F2638F20J Datasheet, PDF (631/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and
generates the stop condition.
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
ICDRE
Generate start
condition
[5]
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W ^[7]
A
1
2
Bit 7 Bit 6
Data 1
IRIC
IRTR
Interrupt
request
Interrupt
request
ICDRT
Address + R/W
ICDRS
Address + R/W
Note: ICDR data
setting timing
Normal operation
Improper operation will
result
User processing
[4] Write BBSY = 1
and SCP = 0
(generate start
condition)
[6] ICDR write
[6] IRIC clearance
Data 1
Data 1
[9] ICDR write
[9] IRIC clearance
Figure 15-8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 581 of 1458