HD64F2638F20J Datasheet, PDF (222/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 7 Bus Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
16-Bit 2-State Access Space: Figures 7-7 to 7-9 show bus timings for a 16-bit 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address.
Wait states cannot be inserted.
Bus cycle
T₁
T₂
φ
Address bus
AS
RD
Read
D15 to D8
Valid
D7 to D0
HWR
Invalid
Write
LWR
D15 to D8
D7 to D0
High
Valid
High impedance
Figure 7-7 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
Page 172 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010