HD64F2638F20J Datasheet, PDF (679/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 16 Controller Area Network (HCAN)
16.2.9 Receive Complete Register (RXPR)
The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags
that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers).
In the case of remote frame reception, the corresponding remote request register (RFPR) is also set
simultaneously.
RXPR
Bit: 15
14
13
12
11
10
9
8
RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Bit: 7
6
5
4
3
2
1
0
RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Note: * Only a write of 1 is permitted, to clear the flag.
Bits 15 to 0—Receive Complete Register (RXPR7 to RXPR0, RXPR15 to RXPR8): These bits
indicate that a receive message has been received normally in the corresponding mailbox.
Bit x: RXPRx
0
1
Description
[Clearing condition]
• Writing 1
(Initial value)
Completion of message (data frame or remote frame) reception in
corresponding mailbox
(x = 15 to 0)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 629 of 1458