HD64F2638F20J Datasheet, PDF (813/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 21A ROM
(H8S/2636 Group)
Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 3: RAMS
0
1
Description
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
(Initial value)
Bits 2, 1 and 0—Flash Memory Area Selection: These bits are used together with bit 3 to select
the flash memory area to be overlapped with RAM (See table 21A-7).
Table 21A-8 Flash Memory Area Divisions (H8S/2636)
Addresses
H'FFE000 to H'FFE3FF
H'000000 to H'0003FF
H'000400 to H'0007FF
H'000800 to H'000BFF
H'000C00 to H'000FFF
*: Don't care
Block Name
RAM area 1 kbyte
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
RAMS
0
1
1
1
1
RAM2
*
0
0
1
1
RAM1
*
0
1
0
1
RAM0
*
*
*
*
*
21A.7.6 Flash Memory Power Control Register (FLPWCR)
Bit: 7
6
5
4
3
2
1
0
PDWND —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode*.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask version only.
These functions cannot be used with the other versions.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 763 of 1458