HD64F2638F20J Datasheet, PDF (688/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 Controller Area Network (HCAN)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 13—Error Passive Interrupt Mask (IMR5): Enables or disables error passive interrupt
requests caused by the transmit/receive error counter.
Bit 13: IMR5
0
1
Description
Error passive interrupt request (ERS0) to CPU by IRR5 enabled
Error passive interrupt request (ERS0) to CPU by IRR5 disabled
(Initial value)
Bit 12—Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning
interrupt requests caused by the receive error counter.
Bit 12: IMR4
0
1
Description
REC error warning interrupt request (OVR0) to CPU by IRR4 enabled
REC error warning interrupt request (OVR0) to CPU by IRR4 disabled
(Initial value)
Bit 11—Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error
warning interrupt requests caused by the transmit error counter.
Bit 11: IMR3
0
1
Description
TEC error warning interrupt request (OVR0) to CPU by IRR3 enabled
TEC error warning interrupt request (OVR0) to CPU by IRR3 disabled
(Initial value)
Bit 10—Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame
reception interrupt requests.
Bit 10: IMR2
0
1
Description
Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled
Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled
(Initial value)
Page 638 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010