HD64F2638F20J Datasheet, PDF (500/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 13 Serial Communication Interface (SCI)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
13.2 Register Descriptions
13.2.1 Receive Shift Register (RSR)
Bit :
7
6
5
4
3
2
1
0
R/W :
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
RSR is a register used to receive serial data.
The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to RDR automatically.
RSR cannot be directly read or written to by the CPU.
13.2.2 Receive Data Register (RDR)
Bit
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
:
R
R
R
R
R
R
R
R
RDR is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR to
RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled.
Since RSR and RDR function as a double buffer in this way, enables continuous receive
operations to be performed.
RDR is a read-only register, and cannot be written to by the CPU.
RDR is initialized to H'00 by a reset, in standby mode, watch mode*, subactive mode*, and
subsleep mode* or module stop mode.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used
with the other versions.
Page 450 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010