HD64F2638F20J Datasheet, PDF (814/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21A ROM
(H8S/2636 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory
power-down mode when the LSI switches to subactive mode. For details, see section 21A.14,
Flash Memory and Power-Down States.
The subactive mode can be used in the U-mask version only.
When writing to this bit in other versions, be sure to write 0.
Bit 7: PDWND
0
1
Description
Transition to flash memory power-down mode enabled
Transition to flash memory power-down mode disabled
(Initial value)
Bits 6 to 0—Reserved: These bits always read 0.
21A.8 On-Board Programming Modes
When pins are set to on-board programming mode and a reset-start is executed, a transition is
made to the on-board programming state in which program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
21A-9. For a diagram of the transitions to the various flash memory modes, see figure 21A-3.
Table 21A-9 Setting On-Board Programming Modes
Mode
Boot mode
User program mode
Expanded mode
Single-chip mode
Expanded mode
Single-chip mode
FWE
1
1
MD2
0
0
1
1
MD1
1
1
1
1
MD0
0
1
0
1
Page 764 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010