HD64F2638F20J Datasheet, PDF (293/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 9 I/O Ports
9.3.2 Register Configuration
Table 9-4 shows the configuration of port 3 registers.
Table 9-4 Port 3 Register Configuration
Name
Port 3 data direction register
Port 3 data register
Port 3 register
Port 3 open drain control register
Notes: 1. Lower 16 bits of the address.
2. Value of bits 5 to 0.
Abbreviation
P3DDR
P3DR
PORT3
P3ODR
R/W Initial Value^*2 Address^*1
W B'**000000 H'FE32
R/W B'**000000 H'FF02
R
Undefined
H'FFB2
R/W B'**000000 H'FE46
Port 3 Data Direction Register (P3DDR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯
⎯ P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Undefined Undefined 0
0
0
0
0
0
⎯
⎯
W
W
W
W
W
W
P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they
become input.
P3DDR is initialized to B'**000000 by a reset and in hardware standby mode. The previous state
is maintained in software standby mode. The pin state is determined by specifying SCI, IIC*,
P3DDR, and P3DR.
Note: * Available when using I²C bus interface as an option in the H8S/2638, H8S/2639, and
H8S/2630 (the product equipped with the I²C bus interface is the W-mask version).
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 243 of 1458