HD64F2638F20J Datasheet, PDF (165/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 5 Interrupt Controller
A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5-2.
IRQnSCA, IRQnSCB
IRQnE
IRQn input
Edge/level
detection circuit
IRQnF
S
Q
R
IRQn interrupt
request
Clear signal
Note: n = 5 to 0
Figure 5-2 Block Diagram of Interrupts IRQ5 to IRQ0
Figure 5-3 shows the timing of setting IRQnF.
φ
IRQn
input pin
IRQnF
Figure 5-3 Timing of Setting IRQnF
The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 16.
Detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 115 of 1458