HD64F2638F20J Datasheet, PDF(1443/1512 Page) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

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HD64F2638F20J Datasheet, PDF (1443/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

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H8S/2639, H8S/2638, H8S/2636,

H8S/2630, H8S/2635 Group

Appendix B Internal I/O Register

SCR0âSerial Control Register 0

SCR1âSerial Control Register 1

SCR2âSerial Control Register 2

Bit

7

6

5

TIE

RIE

TE

Initial value

0

0

0

Read/Write R/W

R/W

R/W

H'FF7A

H'FF82

H'FF8A

SCI0

SCI1

SCI2

4

3

2

1

0

RE MPIE TEIE CKE1 CKE0

0

0

0

0

0

R/W R/W R/W R/W R/W

Clock Enable 1 and 0

0 0 Asynchronous

mode

Internal clock/SCK pin

functions as I/O port

Clocked

Internal clock/SCK pin

synchronous mode functions as serial clock output

1 Asynchronous

mode

Internal clock/SCK pin

functions as clock output*9

Clocked

Internal clock/SCK pin

synchronous mode functions as serial clock output

1 0 Asynchronous

mode

External clock/SCK pin

functions as clock input*10

Clocked

External clock/SCK pin

synchronous mode functions as serial clock input

1 Asynchronous

mode

External clock/SCK pin

functions as clock input*10

Clocked

External clock/SCK pin

synchronous mode functions as serial clock input

Transmit Interrupt Enable

0 Transmit-data-empty interrupt

(TXI) request disabled*1

1 Transmit-data-empty interrupt

(TXI) request enabled

Receive Interrupt Enable

0 Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request disabled*2

1 Receive-data-full interrupt (RXI)

request and receive-error interrupt

(ERI) request enabled

Transmit End Interrupt Enable

0 Transmit-end interrupt (TEI) request disabled*8

1 Transmit-end interrupt (TEI) request enabled*8

Multiprocessor Interrupt Enable

0 Multiprocessor interrupts disabled (normal reception mode)

[Clearing conditions]

â¢ When the MPIE bit is cleared to 0

â¢ When data with MPB = 1 is received

1 Multiprocessor interrupts enabled*7

Receive interrupt (RXI) requests, receive-error interrupt (ERI)

requests, and setting of the RDRF, FER, and ORER flags in

SSR are disabled until data with the multiprocessor bit set to

1 is received

Receive Enable

0 Reception disabled*5

1 Reception enabled*6

Transmit Enable

0 Transmission disabled*3

1 Transmission enabled*4

REJ09B0103-0800 Rev. 8.00

May 28, 2010

Page 1393 of 1458

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