HD64F2638F20J Datasheet, PDF (1370/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
BCRA—Break Control Register A
BCRB—Break Control Register B
H'FE08
H'FE09
Bit
Initial value
Read/Write
7
CMFA
0
R/(W)*
6
CDA
0
R/W
5
4
3
2
1
BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
0
BIEA
0
R/W
PBC
PBC
Break Interrupt Enable
0 PC break interrupts are disabled
1 PC break interrupts are enabled
Break Condition Select
0 0 Instruction fetch is used as break condition
1 Data read cycle is used as break condition
1 0 Data write cycle is used as break condition
1 Data read/write cycle is used as break condition
Break Address Mask Register
0 0 0 All BARA bits are unmasked and included in break conditions
1 BAA0 (lowest bit) is masked, and not included in break conditions
1 0 BAA1, BAA0 (lower 2 bits) are masked, and not included in break conditions
1 BAA2 to BAA0 (lower 3 bits) are masked, and not included in break conditions
1 0 0 BAA3 to BAA0 (lower 4 bits) are masked, and not included in break conditions
1 BAA7 to BAA0 (lower 8 bits) are masked, and not included in break conditions
1 0 BAA11 to BAA0 (lower 12 bits) are masked, and not included in break conditions
1 BAA15 to BAA0 (lower 16 bits) are masked, and not included in break conditions
CPU Cycle/DTC Cycle Select A
0 PC break is performed when CPU is bus master
1 PC break is performed when CPU or DTC is bus master
Condition Match Flag A
0 [Clearing condition]
• When 0 is written to CMFA after reading CMFA = 1
1 [Setting condition]
• When a condition set for channel A is satisfied
Notes: 1. The bit configuration of BCRB is the same as for BCRA.
2. These registers are not available in the H8S/2635 Group.
* Only a 0 may be written to this bit to clear the flag.
Page 1320 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010