HD64F2638F20J Datasheet, PDF (464/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Programmable Pulse Generator (PPG)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
11.3.2 Output Timing
If pulse output is enabled, NDR contents are transferred to PODR and output when the specified
compare match event occurs. Figure 11-3 shows the timing of these operations for the case of
normal output in groups 2 and 3, triggered by compare match A.
φ
TCNT
N
N+1
TGRA
N
Compare match
A signal
NDRH
n
PODRH
m
n
PO8 to PO15
m
n
Figure 11-3 Timing of Transfer and Output of NDR Contents (Example)
Page 414 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010