HD64F2638F20J Datasheet, PDF (408/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
10.4.4 Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 10-5 shows the register combinations used in buffer operation.
Table 10-5 Register Combinations in Buffer Operation
Channel
0
3
Timer General Register
TGR0A
TGR0B
TGR3A
TGR3B
Buffer Register
TGR0C
TGR0D
TGR3C
TGR3D
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10-16.
Compare match signal
Buffer register
Timer general
register
Comparator
Figure 10-16 Compare Match Buffer Operation
TCNT
Page 358 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010