HD64F2638F20J Datasheet, PDF (779/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 19 Motor Control PWM Timer
19.2.9 PWM Buffer Registers 2A to 2D (PWBFR2A to PWBFR2D)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — TDS — — DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
Initial value 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0
Read/Write — — — R/W — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
There are four 16-bit read/write PWBFR2 registers (PWBFR2A to PWBFR2D). When a
PWCYR2 compare match occurs, data is transferred from PWBFR2A to PWDTR2A or
PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or
PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H. The transfer destination is
determined by the value of the TDS bit.
PWBFR2 is initialized to H'EC00 upon reset, and in standby mode, watch mode*, subactive
mode*, subsleep mode*, and module stop mode.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions, and H8S/2635 Group only.
These functions cannot be used with the other versions.
Bits 15 to 13—Reserved: They are always read as 1 and cannot be modified.
Bit 12—Transfer Destination Select (TDS): Bit 12 selects the PWDTR2 register to which data is
to be transferred.
Register
PWBFR2A
PWBFR2B
PWBFR2C
PWBFR2D
Bit 12: TDS
0
1
0
1
0
1
0
1
Description
PWDTR2A selected
PWDTR2E selected
PWDTR2B selected
PWDTR2F selected
PWDTR2C selected
PWDTR2G selected
PWDTR2D selected
PWDTR2H selected
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Bits 11 and 10—Reserved: They are always read as 1 and cannot be modified.
Bits 9 to 0—Duty (DT): Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR2.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 729 of 1458