HD64F2638F20J Datasheet, PDF (746/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 17 A/D Converter
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
17.4.3 Input Sampling and A/D Conversion Time
The A/D converter has an on-chip sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit is set to 1, then starts conversion. Figure 17-5 shows the A/D
conversion timing. Table 17-4 indicates the A/D conversion time.
As indicated in figure 17-5, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 17-4.
In scan mode, the values given in table 17-4 apply to the first conversion time. The values given in
table 17-5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0
in ADCR to give a conversion time of at least 10 µs.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
t_D
t_SPL
t _CONV
Legend:
(1): ADCSR write cycle
(2): ADCSR address
t_D: A/D conversion start delay
t_SPL: Input sampling time
t_CONV: A/D conversion time
Figure 17-5 A/D Conversion Timing
Page 696 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010