HD64F2638F20J Datasheet, PDF (812/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21A ROM
(H8S/2636 Group)
Table 21A-7 Flash Memory Erase Blocks (H8S/2636)
Block (Size)
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (16 kbytes)
EB6 (8 kbytes)
EB7 (8 kbytes)
EB8 (32 kbytes)
EB9 (32 kbytes)
Addresses
H'000000 to H'0003FF
H'000400 to H'0007FF
H'000800 to H'000BFF
H'000C00 to H'000FFF
H'001000 to H'007FFF
H'008000 to H'00BFFF
H'00C000 to H'00DFFF
H'00E000 to H'00FFFF
H'010000 to H'017FFF
H'018000 to H'01FFFF
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
21A.7.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware
standby mode. It is not initialized by software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 21A-8. To ensure correct operation of the
emulation function, the ROM for which RAM emulation is performed should not be accessed
immediately after this register has been modified. Normal execution of an access immediately
after register modification is not guaranteed.
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
—
—
— RAMS RAM2 RAM1 RAM0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Bits 7 and 6—Reserved: These bits always read 0.
Bits 5 and 4—Reserved: Only 0 may be written to these bits.
Page 762 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010