HD64F2638F20J Datasheet, PDF (983/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F,
HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F]
23A.2.3 Low-Power Control Register (LPWRCR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
DTON LSON NESEL SUBSTP RFCUT ⎯
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
1
STC1
0
R/W
0
STC0
0
R/W
The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes.
The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not
initialized in software standby mode. The following describes bits 7 to 2. For details of other bits,
see section 22A.2.2, Low-Power Control Register (LPWRCR).
Bits 7 to 3—Reserved: Bits DTON, LSON, NESEL, SUBSTP and RFCUT must always be
written with 0, as this version does not support subclock operation.
Bit 2—Reserved: Only write 0 to this bit.
23A.2.4 Timer Control/Status Register (TCSR)
Bit
:
7
6
OVF WT/IT
Initial value :
0
0
R/W
: R/(W)* R/W
Note: * Only write 0 to clear the flag.
5
TME
0
R/W
4
PSS
0
R/W
3
2
RST/NMI CKS2
0
0
R/W R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode.
Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer
Control/Status Register (TCSR).
The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized
in software standby mode.
Bit 4—Reserved: The PSS bit must always be written with 0 since no subclock functions are
available in versions other than the U-mask and W-mask versions.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 933 of 1458