HD64F2638F20J Datasheet, PDF (609/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 15 I²C Bus Interface [Option]
(Only for the H8S/2638, H8S/2639, and H8S/2630)
15.2.5 I²C Bus Control Register (ICCR)
Bit
:7
ICE
Initial value : 0
R/W
: R/W
6
5
IEIC MST
0
0
R/W R/W
4
TRS
0
R/W
3
ACKE
0
R/W
2
BBSY
0
R/W
1
IRIC
0
R/(W)*
0
SCP
1
W
Note: * Only 0 can be written, for flag clearing.
ICCR is an 8-bit readable/writable register that enables or disables the I²C bus interface, enables or
disables interrupts, selects master or slave mode and transmission or reception, enables or disables
acknowledgement, confirms the I²C bus interface bus status, issues start/stop conditions, and
performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset and in hardware standby mode.
Bit 7—I²C Bus Interface Enable (ICE): Selects whether or not the I²C bus interface is to be
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
operations are enabled. When ICE is cleared to 0, the I²C bus interface module is halted and its
internal states are cleared.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.
Bit 7
ICE
0
1
Description
I²C bus interface module disabled, with SCL and SDA signal pins set to port function
(Initial value)
I²C bus interface module internal states initialized
SAR and SARX can be accessed
I²C bus interface module enabled for transfer operations (pins SCL and SCA are
driving the bus)
ICMR and ICDR can be accessed
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 559 of 1458