HD64F2638F20J Datasheet, PDF (489/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 12 Watchdog Timer
12.3 Operation
12.3.1 Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software
must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. This ensures that TCNT does not overflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system malfunction or other
error, an internal reset is issued, in the case of WDT0, if the RSTE bit in RSTCSR is set to 1.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system
clock periods (516φ) (515 or 516 clock periods when the clock source is φ/SUB* (PSS = 1)). This
is illustrated in figure 12-4 (b).
An NMI request from the watchdog timer and an interrupt request from the NMI pin are both
treated as having the same vector. So, avoid handling an NMI request from the watchdog timer
and an interrupt request from the NMI pin at the same time.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used
with the other versions.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 439 of 1458