HD64F2638F20J Datasheet, PDF (92/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
2.6 Instruction Set
2.6.1 Overview
The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2-1.
Table 2-1 Instruction Classification
Function
Instructions
Size Types
Data transfer
MOV
POP^*1, PUSH^*1
LDM^*5, STM^*5
MOVFPE^*3, MOVTPE^*3
BWL 5
WL
L
B
Arithmetic
operations
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
BWL 23
B
INC, DEC
BWL
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
BW
EXTU, EXTS
WL
TAS^*4
B
MAC, LDMAC, STMAC, CLRMAC
—
Logic operations AND, OR, XOR, NOT
BWL 4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B
14
BIAND, BOR, BIOR, BXOR, BIXOR
Branch
Bcc^*2, JMP, BSR, JSR, RTS
—
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
9
Block data transfer EEPMOV
—
1
Total: 69 types
Legend:
B: Byte
W: Word
L: Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Not available in the chip.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
5. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
Page 42 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010