HD64F2638F20J Datasheet, PDF (365/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 10 16-Bit Timer Pulse Unit (TPU)
Bits 7 to 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT
counter clearing source.
Channel
0, 3
Bit 7
CCLR2
0
1
Bit 6
CCLR1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
0
1
0
1
Description
TCNT clearing disabled
(Initial value)
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation ^*1
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
capture ^*2
TCNT cleared by TGRD compare match/input
capture ^*2
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation ^*1
Bit 7
Bit 6
Channel Reserved^*3 CCLR1
Bit 5
CCLR0
Description
1, 2, 4, 5 0
0
0
TCNT clearing disabled
(Initial value)
1
TCNT cleared by TGRA compare match/input
capture
1
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation ^*1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 315 of 1458