HD64F2638F20J Datasheet, PDF (954/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 22A Clock Pulse Generator
(H8S/2636 Group, H8S/2638 Group, H8S/2630 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
22A.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR and LPWRCR. Table 22A-1 shows the register
configuration.
Table 22A-1 Clock Pulse Generator Register
Name
Abbreviation R/W
System clock control register
SCKCR
R/W
Low-power control register
LPWRCR
R/W
Note:* Lower 16 bits of the address.
Initial Value
H'00
H'00
Address*
H'FDE6
H'FDEC
22A.2 Register Descriptions
22A.2.1 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
PSTOP ⎯
⎯
⎯
Initial value:
0
0
0
0
R/W
: R/W
⎯
⎯
⎯
3
STCS
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
0
SCK0
0
R/W
SCKCR is an 8-bit readable/writable register that performs φ clock output control and medium-
speed mode control, selection of operation when the PLL circuit frequency multiplication factor is
changed, and medium-speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls φ output. See section 23A.8, 23B.12, φ Clock Output Disable Function for details.
Bit 7
PSTOP
0
1
Description
Normal Operating
State
φ output (initial value)
Fixed high
Sleep Mode
φ output
Fixed high
Software
Standby Mode
Fixed high
Fixed high
Hardware
Standby Mode
High impedance
High impedance
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Page 904 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010