HD64F2638F20J Datasheet, PDF (454/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Programmable Pulse Generator (PPG)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or
disable pulse output on a bit-by-bit basis.
Bits 7 to 0
NDER7 to NDER0
0
1
Description
Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not
transferred to POD7 to POD0)
(Initial value)
Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to
POD7 to POD0)
11.2.2 Output Data Registers H and L (PODRH, PODRL)
PODRH
Bit
:
Initial value :
R/W
:
7
POD15
0
R/(W)^*
6
POD14
0
R/(W)^*
5
POD13
0
R/(W)^*
4
POD12
0
R/(W)^*
3
POD11
0
R/(W)^*
2
POD10
0
R/(W)^*
1
POD9
0
R/(W)^*
0
POD8
0
R/(W)^*
PODRL
Bit
:
Initial value :
R/W
:
7
POD7
0
R/(W)^*
6
POD6
0
R/(W)^*
5
POD5
0
R/(W)^*
4
POD4
0
R/(W)^*
3
POD3
0
R/(W)^*
2
POD2
0
R/(W)^*
1
POD1
0
R/(W)^*
0
POD0
0
R/(W)^*
Note: * A bit that has been set for pulse output by NDER is read-only.
PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse
output. However, the chip has no pins corresponding to PODRL.
Page 404 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010