HD64F2638F20J Datasheet, PDF (1480/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix C I/O Port Block Diagrams
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
*2
P32
*1
*3
Reset
R
Q
D
P32DDR
C
WDDR3
Reset
R
Q
D
P32DR
C
WDR3
Reset
R
Q
D
P32ODR
C
WODR3
RODR3
RDR3
IIC1 module^*4
SDA1 output
IIC1 output enable
SDA1 input
SCI module
Serial clock output
enable
Serial clock output
Serial clock input
enable
RPOR3
Serial clock input
Interrupt controller
IRQ4 interrupt input
Legend:
WDDR3: Write to P3DDR
WDR3: Write to P3DR
WODR3: Write to P3ODR
RDR3: Read P3DR
RPOR3: Read port 3
RODR3: Read P3ODR
Notes: 1. Priority order: IIC output > Serial clock output > DR output
2. Output enable signal
3. Open drain control signal
4. The IIC1 module is available as an option in the
H8S/2638, H8S/2639, H8S/2630.
Figure C-2 (c) Port 3 Block Diagram (Pin P32)
Page 1430 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010