HD64F2638F20J Datasheet, PDF (1442/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Appendix B Internal I/O Register
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
ICSR0—I²C Bus Status Register
ICSR1—I²C Bus Status Register
H'FF79
H'FF81
IIC0
IIC1
Bit
:
Initial value :
R/W
:
7
ESTP
0
R/(W)*
6
STOP
0
R/(W)*
5
IRTR
0
R/(W)*
4
AASX
0
R/(W)*
3
AL
0
R/(W)*
2
AAS
0
R/(W)*
1
ADZ
0
R/(W)*
0
ACKB
0
R/W
Acknowledge bit
0 When receiving, 0 is output at acknowledge output timing.
When transmitting, this bit shows that an acknowledge (0)
has not been sent from the receiving device.
1 When receiving, 1 is output at acknowledge output timing.
When transmitting, this bit shows that an acknowledge (1)
has been sent from the receiving device.
General call address confirmation flag
0 General call address not confirmed
[Clearings]
(1) When data is written to ICDR (when sending), or when data is
read from ICDR (when receiving);
(2) When 0 is written after reading ADZ=1;
(3) In master mode.
1 General call address confirmation
[Setting]
• When general call address is detected is in slave receive mode and
FSX = 0 or FS = 0).
Slave address confirmation flag
0 Slave address or general call address not confirmed
[Clearings]
(1) When data is written to ICDR (when sending), or when data is
read from ICDR (when receiving);
(2) When 0 is written after reading AAS=1;
(3) In master mode.
1 Slave address or general call address confirmed
[Setting]
• When slave address or general call address is detected in slave
receive mode and FS = 0.
Arbitration lost flag
0 Secure bus.
[Clearings]
(1) When data is written to ICDR (when sending), or when data is read (when
receiving);
(2) When 0 is written after reading AL=1.
1 Bus arbitration lost
[Settings]
(1) When there is a mismatch between internal SDA and SDA pin at rise in SCL
in master transmit mode;
(2) When the internal SCL level is HIGH at the fall in SCL in master transmit mode.
2nd slave address confirmation flag
0 2nd slave address not confirmed
[Clearings]
(1) When 0 is written after reading AASX=1;
(2) When start conditions are detected;
(3) In master mode.
1 2nd slave address confirmed
[Setting]
• When 2nd slave address is detected in slave receive mode and FSX = 0.
I²C bus interface continuous transmit and receive interrupt request flag
0 Transmit wait state, or transmitting
[Clearings]
(1) When 0 written after reading IRTR=1;
(2) When IRIC flag is cleared to 0.
1 Continuous transmit state
[Settings]
• In I2C bus interface slave mode
When 1 is set in TDRE or RDRF flag when AASX=1.
• In other than I2C bus interface slave mode
When TDRE or RDRF flag is set to 1.
Normal end condition detection flag
0 No normal end condition
[Clearings]
(1) When 0 is written after reading STOP=1;
(2) When IRIC flag is cleared to 0.
1 Normal end condition detected in slave mode in I²C bus format
[Setting]
On detection of stop condition on completion of sending frame.
• No meaning when in other than slave mode in I2C bus format
Error stop condition detection flag
0 No error stop condition
[Clearings]
(1) When 0 written after reading ESTP=1;
(2) When IRIC flag is cleared to 0.
1 • Error stop condition detected in slave mode in I2C bus format
[Setting]
On detection of stop condition while sending frame.
• No meaning when in other than slave mode in I2C bus format
Notes: This register is valid only on the H8S/2638, H8S/2639, or H8S/2630 with the I²C bus interface option added.
* Only 0 can be written to these bits (to clear these flags).
Page 1392 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010