HD64F2638F20J Datasheet, PDF (1207/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Appendix B Internal I/O Register
Register
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
Data Bus
Width
H'FF90 ADDRAH AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
A/D
8
H'FF91 ADDRAL AD1
AD0
—
—
—
—
—
—
H'FF92 ADDRBH AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'FF93 ADDRBL AD1
AD0
—
—
—
—
—
—
H'FF94 ADDRCH AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'FF95 ADDRCL AD1
AD0
—
—
—
—
—
—
H'FF96 ADDRDH AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'FF97 ADDRDL AD1
AD0
—
—
—
—
—
—
H'FF98 ADCSR ADF
ADIE
ADST
SCAN
CH3
CH2
CH1
CH0
H'FF99 ADCR
H'FFA2 TCSR1
(read/write)
TRGS1
OVF
TRGS0
WT/IT
—
TME
—
PSS*¹
CKS1
CKS0
RST/NMI CKS2
—
CKS1
—
CKS0
WDT1 16
H'FFA3 TCNT1
(read)
H'FFA4 DADR0
D/A0, 1 8
H'FFA5 DADR1
H'FFA6 DACR01 DAOE1 DAOE0 DAE
—
—
—
—
—
H'FFA8 FLMCR1 FWE
SWE
ESU
PSU
EV
PV
E
P
FLASH 8
H'FFA9 FLMCR2 FLER
—
—
—
—
—
—
—
H'FFAA EBR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
H'FFAB EBR2
—
—
EB13*⁸
EB12*⁸
EB11*⁶
EB10*⁵
EB9
EB8
H'FFAC FLPWCR PDWND*² —
—
—
—
—
—
—
H'FFB0 PORT1 P17
P16
P15
P14
P13
P12
P11
P10
PORT
8
H'FFB2 PORT3 —
—
P35
P34
P33
P32
P31
P30
H'FFB3 PORT4 P47
P46
P45
P44
P43
P42
P41
P40
H'FFB8 PORT9 —
—
—
—
P93
P92
P91
P90
H'FFB9 PORTA —
—
—
—
PA3
PA2
PA1
PA0
H'FFBA PORTB PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
H'FFBB PORTC PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
H'FFBC PORTD PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
H'FFBD PORTE PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
H'FFBE PORTF PF7
PF6
PF5
PF4
PF3
—
—
PF0
Notes:
1. Bit 4 (PSS) in TCSR of WDT1 is valid in the U-mask and W-mask versions, and H8S/2635 Group. In versions other
than the U-mask and W-mask versions, and H8S/2635 Group, however, the PSS bit must always be written with 0
since no subclock functions are available.
2. Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in versions other than the
U-mask and W-mask versions, and H8S/2635 Group.
Subclock functions may be used with the U-mask and W-mask versions, and H8S/2635 Group.
3. Bits DTON, LSON, NESEL, and SUBSTP in LPWRCR are valid in the U-mask and W-mask versions, and H8S/2635
Group. In versions other than the U-mask and W-mask versions, and H8S/2635 Group, however, these bits must
always be written with 0 since no subclock functions are available.
4. An I²C bus interface can only be added to the H8S/2638, H8S/2639, and H8S/2630. Therefore, IIC related registers
are valid only in the H8S/2638, H8S/2639, and H8S/2630.
5. This bit is reserved in the H8S/2636.
6. This bit is reserved in the H8S/2636 and H8S/2635.
7. These bits are not available in the H8S/2635 Group.
8. These bits are reserved in the H8S/2636, H8S/2638, H8S/2639, and H8S/2635. These bits are valid in the
H8S/2630 only.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 1157 of 1458