HD64F2638F20J Datasheet, PDF (816/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 21A ROM
(H8S/2636 Group)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Start
Set pins to boot mode
and execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
Chip measures low period of
H'00 data transmitted by host
Chip calculates bit rate and sets
value in bit rate register
After bit rate adjustment, chip
transmits one H'00 data byte to
host to indicate end of adjustment
Host confirms normal reception
of bit rate adjustment end
indication (H'00), and transmits
one H'55 data byte
After receiving H'55,
LSI transmits one H'AA
data byte to host
Host transmits number
of programming control program
bytes (N), upper byte followed
by lower byte
Chip transmits received number
of bytes to host as verify data
(echo-back)
n=1
Host transmits programming control
program sequentially in byte units
Chip transmits received
programming control program to
host as verify data (echo-back)
Transfer received programming
control program to on-chip RAM
n = N?
No
Yes
End of transmission
Check flash memory data, and
if data has already been written,
erase all blocks
After confirming that all flash
memory data has been erased,
chip transmits one H'AA data
byte to host
Execute programming control
program transferred to on-chip RAM
n+1→n
Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is
transmitted as an erase error, and the erase operation and subsequent operations
are halted.
Page 766 of 1458
Figure 21A-8 Boot Mode Execution Procedure
REJ09B0103-0800 Rev. 8.00
May 28, 2010