HD64F2638F20J Datasheet, PDF (444/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T₂ state of a TGR write cycle, the input capture operation takes precedence and the write to
TGR is not performed.
Figure 10-54 shows the timing in this case.
φ
Address
TGR write cycle
T₁
T₂
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 10-54 Contention between TGR Write and Input Capture
Page 394 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010