HD64F2638F20J Datasheet, PDF (208/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 7 Bus Controller
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
7.2.4 Bus Control Register H (BCRH)
Bit
:
7
6
5
4
3
2
1
0
ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 ⎯
⎯
⎯
Initial value :
1
1
0
1
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle
insertion, and the memory interface for area 2 to 5, and 0.
BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
0
1
Description
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
(Initial value)
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed .
Bit 6
ICIS0
0
1
Description
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
(Initial value)
Page 158 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010