HD64F2638F20J Datasheet, PDF (196/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 6 PC Break Controller (PBC)
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
SLEEP instruction
execution
PC break exception
handling
Execution of instruction
after sleep instruction
(A)
SLEEP instruction
execution
SLEEP instruction
execution
SLEEP instruction
execution
System clock
→ subclock*
Direct transition*
exception handling
PC break exception
handling
Subclock* →
system clock,
oscillation settling time
Direct transition*
exception handling
Transition to
respective mode
(D)
Subactive*
mode
PC break exception
handling
High-speed
(medium-speed)
mode
Execution of instruction
after sleep instruction
(B)
Execution of instruction
after sleep instruction
(C)
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available
in the U-mask and W-mask versions only.
Figure 6-2 Operation in Power-Down Mode Transitions
6.3.5 PC Break Operation in Continuous Data Transfer
If a PC break interrupt is generated when the following operations are being performed, exception
handling is executed on completion of the specified transfer.
(1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction:
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
(2) When a PC break interrupt is generated at a DTC transfer address:31
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
Page 146 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010