HD64F2638F20J Datasheet, PDF (980/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 23A Power-Down Modes [HD64F2636F, HD64F2638F, HD6432636F,
HD6432638F, HD64F2630F, HD6432630F, HD64F2635F, HD6432635F, HD6432634F]
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
23A.2 Register Descriptions
23A.2.1 Standby Control Register (SBYCR)
Bit
:
7
6
5
4
3
2
1
0
SSBY STS2 STS1 STS0 OPE
⎯
⎯
⎯
Initial value :
0
1
0
1
1
0
0
0
R/W
: R/W
R/W R/W
R/W R/W
⎯
⎯
⎯
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'58 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by
executing the SLEEP instruction, the operating mode is determined in combination with other
control bits.
Note that the value of the SSBY bit does not change even when shifting between modes using
interrupts.
Bit 7
SSBY
0
1
Description
Shifts to sleep mode when the SLEEP instruction is executed in high-speed
mode or medium-speed mode.
(Initial value)
Shifts to software standby mode when the SLEEP instruction is executed in high-
speed mode or medium-speed mode.
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time
for clock stabilization when shifting to high-speed mode or medium-speed mode by using a
specific interrupt or command to cancel software standby mode. With a quartz oscillator (Table
23A-5), select a wait time of 8ms (oscillation stabilization time) or more, depending on the
operating frequency. With an external clock, select a standby time of 2 ms or more (PLL oscillator
settling time), based on the operating frequency.
Page 930 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010