HD64F2638F20J Datasheet, PDF (775/1512 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 19 Motor Control PWM Timer
Bit 12—Output Terminal Select (OTS): Bit 12 selects the pin used for PWM output according
to the value in bit 12 in the buffer register that is transferred by a PWCYR1 compare match.
Unselected pins output a low level (or a high level when the corresponding bit in PWPR1 is set to
1).
Register
PWDTR1A
PWDTR1C
PWDTR1E
PWDTR1G
Bit 12: OTS
0
1
0
1
0
1
0
1
Description
PWM1A output selected
PWM1B output selected
PWM1C output selected
PWM1D output selected
PWM1E output selected
PWM1F output selected
PWM1G output selected
PWM1H output selected
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Bits 11 and 10—Reserved: These bits cannot be read from or written to.
Bits 9 to 0—Duty (DT): Bits 9 to 0 set the PWM output duty according to the values in bits 9 to 0
in the buffer register that is transferred by a PWCYR1 compare match. A high level (or a low level
when the corresponding bit in PWPR1 is set to 1) is output from the time PWCNT1 is cleared by a
PWCYR1 compare match until a PWDTR1 compare match occurs. When all the bits are 0, there
is no high-level output period (no low-level output period when the corresponding bit in PWPR1
is set to 1).
PWCNT1
(lower 10 bits)
PWCYR1
(lower 10 bits)
PWDTR1
(lower 10 bits)
PWM output on
selected pin
PWM output on
unselected pin
0
1
Compare match
M−2 M−1 M
N
M
N−1 0
Figure 19-4 Duty Register Compare Match (OPS = 0 in PWPR1)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page 725 of 1458