SH7280 Datasheet, PDF(994/1726 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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SH7280 Datasheet, PDF (994/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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Section 19 I2C Bus Interface 3 (IIC3)

19.6 Data Transfer Using DTC

In the I2C bus format, the slave device and transfer direction are selected through the slave address

and R/W bit, and data reception is confirmed and the last frame is indicated through the

acknowledge bit. Therefore, when the DTC is used to transfer data continuously, the DTC

processing should be done in combination with the CPU processing activated by interrupts.

Table 19.5 shows an example of I2C data transfer using the DTC. This example assumes that the

transfer data count is determined in advance in slave mode.

Table 19.5 Example of Data Transfer Using DTC

Item

Master Transmit

Mode

Master Receive

Mode

Slave Transmit

Mode

Slave Receive

Mode

Slave address + R/W Transmitted by DTC Transmitted by CPU Received by CPU

bit transmit/receive (ICDR writing)

(ICDR writing)

(ICDR reading)

Received by CPU

(ICDR reading)

Dummy data read ï£§

Processed by CPU ï£§

ï£§

(ICDR writing)

Main data

transmit/receive

Transmitted by DTC Received by DTC

(ICDR writing)

(ICDR reading)

Transmitted by DTC Received by DTC

(ICDR writing)

(ICDR reading)

Last frame

processing

Not necessary

Received by CPU

(ICDR reading)

Not necessary

Received by CPU

(ICDR reading)

DTC transfer data

frame count setting

Transmission: Actual Reception; Actual

data count + 1

data count

(+1 is required for

the slave address +

R/W bit transfer)

Transmission; Actual Reception; Actual

data count

data count

Rev. 1.00 Jun. 26, 2008 Page 964 of 1692

REJ09B0393-0100

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