SH7280 Datasheet, PDF (311/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Bit
21, 20
Bit Name
BST[1:0]
Initial
Value
00
R/W Description
R/W Burst Count Specification
Specify the burst count for 16-byte access. These bits
must not be set to B'11.
Bus Width BST[1:0] Burst count
8 bits
00
16 burst × one time
01
4 burst × four times
16 bits
00
8 burst × one time
01
2 burst × four times
10
4-4 or 2-4-2 burst
19, 18 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
17, 16 BW[1:0]
00
R/W Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or subsequent access cycles in
burst access.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Jun. 26, 2008 Page 281 of 1692
REJ09B0393-0100