SH7280 Datasheet, PDF(1027/1726 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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SH7280 Datasheet, PDF (1027/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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Section 20 A/D Converter (ADC)

20.4.3 Input Sampling and A/D Conversion Time

The A/D converter has built-in sample-and-hold circuits. Channels 0 to 2 can be simultaneously

sampled as one group when the SH bit in ADBYPSCR_0 is set to 1. This group is referred to as

Group A (GrA) (in table 20.5). When the SH bit is cleared to 0, these channels are sampled

individually in the same way as other channels.

Setting the ADST bit to 1 starts A/D conversion. The A/D conversion time (tCONV) from the

beginning to the end of conversion is determined by the following five time factors (figure 20.10):

the A/D conversion start delay time (tD), sampling time (tSPLSH), offset canceling processing time

(tOFC), sampling time (tSPL), and A/D conversion processing time; the A/D conversion time (tCONV) is

the sum of these times. tSPLSH and tOFC can be reduced according to the following procedures.

To reduce t , SPLSH clear the SH bit in ADBYPSCR_0 to 0 (initial value). Note that when GrA

channels should be sampled simultaneously, the SH bit should be set to 1 to provide appropriate

t . SPLSH tSPLSH indicates the time required for the operation of the sample-and-hold circuits dedicated

to channels 0 to 2 and it does not depend on the number of channels sampled simultaneously.

To reduce tOFC, set the OFC bit in ADBYPSCR_0 to 1. Note that when highly accurate A/D

conversion is required, the OFC bit should be cleared to 0 (initial value) to provide appropriate

tOFC. In most cases, it is recommended to clear the OFC bit to 0 (initial value).

In continuous scan mode, the A/D conversion time (tCONV) given in table 20.6 applies to the

conversion time of the first cycle. The conversion time of the second and subsequent cycles is

expressed as (tCONV â tD + 6).

Table 20.6 shows the state for the AÏ1 clock. The value is calculated by multiplying the cycle

time of AÏ and the number of the state. The AÏ should always be set to PÏ or greater (PÏ â¤ AÏ)

value.

Rev. 1.00 Jun. 26, 2008 Page 997 of 1692

REJ09B0393-0100

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