SH7280 Datasheet, PDF (1371/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
Initial
Bit
Bit Name Value R/W Description
2
EP0sRDFN 0
W
EP0s Read Complete
Write 1 to this bit after EP0s command FIFO data has
been read. Writing 1 to this bit enables
transmission/reception of data in the following data
stage. A NACK handshake is returned in response to
transmit/receive requests from the host in the data
stage until 1 is written to this bit.
1
EP0oRDFN 0
W
EP0o Read Complete
Writing 1 to this bit after one packet of data has been
read from the endpoint 0 transmit FIFO buffer
initializes the FIFO buffer, enabling the next packet to
be received.
0
EP0iPKTE 0
W
EP0i Packet Enable
After one packet of data has been written to the
endpoint 0 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
Rev. 1.00 Jun. 26, 2008 Page 1341 of 1692
REJ09B0393-0100