SH7280 Datasheet, PDF (1523/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 28 Power-Down Modes
Section 28 Power-Down Modes
In power-down modes, operation of some of the internal peripheral modules and of the CPU stops.
This leads to reduced power consumption. These modes are canceled by a reset or interrupt.
28.1 Features
28.1.1 Power-Down Modes
This LSI has the following power-down modes and function:
1. Sleep mode
2. Software standby mode
3. Module standby function
Table 28.1 shows the transition conditions for entering the modes from the program execution
state, as well as the CPU and peripheral module states in each mode and the procedures for
canceling each mode.
Table 28.1 States of Power-Down Modes
State*
Power-Down
Mode
CPU
On-Chip
Transition Conditions CPG CPU Register Memory
On-Chip
Peripheral
Modules
External
Memory
Canceling
Procedure
Sleep mode
Execute SLEEP
Runs
instruction with STBY bit
cleared to 0 in STBCR
Halts
Held
Runs
(RAM)
Halts
(Flash memory)
Runs
Auto-
refreshing
• Interrupt
• Manual reset
• Power-on reset
• DMA address
error
Software
standby mode
Execute SLEEP
Halts
instruction with STBY bit
set to 1 in STBCR
Halts
Held
Halts
(contents are
held)
Halts
Self-
refreshing
• Power-on reset
Module standby
function
Set the MSTP bits in
STBCR2, STBCR3,
STBCR4, STBCR5, and
STBCR6 to 1
Runs
Runs
Held
Specified
module halts
(contents are
held)
Specified
module halts
Auto-
refreshing
• Clear MSTP bit
to 0
• Power-on reset
(only for H-UDI,
UBC, and
DMAC)
Note: * The pin state is retained or set to high impedance. For details, see appendix A, Pin
States.
Rev. 1.00 Jun. 26, 2008 Page 1493 of 1692
REJ09B0393-0100