SH7280 Datasheet, PDF (959/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 19 I²C Bus Interface 3 (IIC3)
19.3.1 I²C Bus Control Register 1 (ICCR1)
ICCR1 is an 8-bit readable/writable register that enables or disables the I²C bus interface 3,
controls transmission or reception, and selects master or slave mode, transmission or reception,
and transfer clock frequency in master mode.
ICCR1 is initialized to H'00 by a power-on reset.
Bit: 7
6
5
ICE RCVD MST
Initial value: 0
0
0
R/W: R/W R/W R/W
4
TRS
0
R/W
3
0
R/W
2
1
CKS[3:0]
0
0
R/W R/W
0
0
R/W
Initial
Bit
Bit Name Value R/W Description
7
ICE
0
R/W I²C Bus Interface 3 Enable
0: This module is halted. (SCL and SDA pins function
as ports.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6
RCVD
0
R/W Reception Disable
Enables or disables the next operation when TRS is 0
and ICDRR is read. In master receive mode, when
ICDRR cannot be read before the rising edge of the
8th clock of SCL, set RCVD to 1 so that data is
received in byte units.
0: Enables next reception
1: Disables next reception
Rev. 1.00 Jun. 26, 2008 Page 929 of 1692
REJ09B0393-0100