SH7280 Datasheet, PDF (116/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 4 Clock Pulse Generator (CPG)
4.4.4 Oscillation Stop Detection Control Register (OSCCR)
OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects
flag status output to an external pin. OSCCR can be accessed only in byte units.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
OSC
STOP
-
OSC
ERS
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W
Bit
7 to 3
2
1
0
Bit Name

Initial
Value
All 0
OSCSTOP 0

0
OSCERS 0
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Oscillation Stop Detection Flag
[Setting condition]
• When a stop in the clock input is detected during
normal operation
[Clearing condition]
• By a power-on reset input through the RES pin
Reserved
This bit is always read as 0. The write value should
always be 0.
Oscillation Stop Detection Flag Output Select
Selects whether to output the oscillation stop
detection flag signal through the WDTOVF pin.
0: Outputs only the WDT overflow signal through the
WDTOVF pin
1: Outputs the WDT overflow signal and oscillation
stop detection flag signal through the WDTOVF
pin
Rev. 1.00 Jun. 26, 2008 Page 86 of 1692
REJ09B0393-0100