SH7280 Datasheet, PDF (1025/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
A/D conversion execution
ADST
ADST set*
ADST cleared*
ADF
AN0
AN1
AN2
AN3
ADDR0
ADDR1
ADF cleared*
Stop
Waiting for
conversion
S
A/D
conversion
Waiting for conversion
S
A/D
conversion
Waiting for conversion S
Waiting for
conversion
(1)
(2)
Waiting for conversion
Waiting for
conversion
S
H
A/D
conversion
(1)
Waiting for conversion
Waiting for
conversion
S
H
A/D
conversion
Stop
Waiting for
conversion
S
Waiting for
conversion
(2)
A/D
conversion
(1)
Waiting for conversion
A/D
conversion
(2)
Waiting for
conversion
A/D conversion result (AN0)
(1)
A/D conversion result (AN0)
(2)
ADDR2
ADDR3
[Legend]
OFC: Offset canceling processing
S:
Sampling
H:
Holding
Note: * Instruction execution by software
A/D conversion result (AN2)
(1)
A/D conversion result (AN3)
(1)
[ADBYPSCR_0 settings]
OFC bit = 1
SH bit = 0
A/D conversion result (AN2)
(2)
A/D conversion result (AN3)
(2)
Figure 20.8 Example 3 of A/D Converter Operation (Continuous Scan Mode,
Sample-and-Hold Circuit Enabled, and Offset Canceling Circuit Disabled)
Rev. 1.00 Jun. 26, 2008 Page 995 of 1692
REJ09B0393-0100