SH7280 Datasheet, PDF (1667/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 31 Electrical Characteristics
CK
WDTOVF
t_WOVD
t_WOVD
Figure 31.44 Watchdog Timer Timing
31.3.9 SCI Module Timing
Table 31.13 SCI Module Timing
Conditions: V_CC = 3.0 to 5.5 V, AV_CC = AVREF = 4.5 to 5.5 V,
V_SS = PLLV_SS = AVREFVSS = AV_SS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Item
Symbol Min.
Input clock cycle (asynchronous)
t_Scyc
Input clock cycle (clocked synchronous) t_Scyc
Input clock pulse width
t
SCKW
Input clock rise time
t
SCKr
Input clock fall time
t
SCKf
Transmit data delay time (asynchronous) t
TXD
Receive data setup time
t_RXS
Receive data hold time
t_RXH
Transmit data delay time (clocked
t_TXD
Receive data setup time ^synchronous) t_RXS
Receive data hold time
t_RXH
Note:
t
pcyc
indicates
peripheral
clock
(Pφ)
cycle.
4
6
0.4



4t_pcyc
4t_pcyc

3t_pcyc + 20
3t_pcyc + 20
Max.


0.6
1.5
1.5
4t + 20
pcyc


3t_pcyc + 20
–
–
Unit
t_pcyc
t_pcyc
t
scyc
t
pcyc
t
pcyc
ns
ns
ns
ns
ns
ns
Figure
Figure 31.45
Figure 31.46
Rev. 1.00 Jun. 26, 2008 Page 1637 of 1692
REJ09B0393-0100