SH7280 Datasheet, PDF(1375/1726 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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SH7280 Datasheet, PDF (1375/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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Section 25 USB Function Module

Initial

Bit

Bit Name Value

R/W Description

0

EP1DMAE*2 0

R/W Endpoint 1 DMA/DTC Transfer Enable

When this bit is set, DMA/DTC transfer is enabled

from the endpoint 1 receive FIFO buffer to memory. If

there is at least one byte of receive data in the FIFO

buffer, a transfer request is asserted for the DMAC or

DTC. In DMA/DTC transfer, when all the received

data is read, EP1 is read automatically and the

completion trigger operates.

Also, as EP1-related interrupt requests to the CPU

are not automatically masked, interrupt requests

should be masked as necessary in the interrupt

enable register.

Notes: 1. Before setting this bit, set the DME bit in DMAOR to start DMA transfer or set the

DTCE0 bit in DTCERA to start DTC transfer.

2. Before setting this bit, set the DME bit in DMAOR to start DMA transfer or set the

DTCE1 bit in DTCERA to start DTC transfer.

Rev. 1.00 Jun. 26, 2008 Page 1345 of 1692

REJ09B0393-0100

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