SH7280 Datasheet, PDF (1400/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
USB function
IN token reception
Valid data
in EP2 FIFO?
YES
NO
NACK
Data transmission to host
ACK
DMA function
Application
Set I[3:0] bits in SR
Set bits 15 to 12 in IPR06
(enable interrupts)
Set transfer information
(SAR_0, DAR_0, DMATCR_0,
CHCR_0, DMAOR, DMARS0)
NO
Is there data
for transmission
to host?
YES
Enable EP2 FIFO empty interrupt
(USBIER0/EP2 EMPTY = 1)
Space
in EP2 FIFO?
NO
YES
Set EP2 empty status
(USBIFR0/EP2
EMPTY = 1)
Clear EP2 empty status
(USBIFR0/EP2
EMPTY = 0)
Interrupt request to CPU
Activate DMA
DMA transfer
request
Disable EP2 FIFO
empty interrupt
(USBIER0/EP2 EMPTY = 0)
Set EP2DMAE bit in USBDMAR
to 1
Interrupt request
DMA transfer end
to CPU
Clear EP2DMAE bit in USBDMAR
Set TE bit in CHCR
to 0 and clear TE bit in CHCR
Data transfer end
interrupt
Write 1 to EP2 packet
[1]
enable bit
(USBTRG/EP2 PKTE = 1)
[1] When the transmit data size is a multiple of 64 bytes, this step can be omitted.
Figure 25.20 Example of DMA Transfer (Channel 0) for Bulk-IN Transfer (EP2)
(When Transmit Data Size Cannot be Determined Before Receiving IN Token)
Rev. 1.00 Jun. 26, 2008 Page 1370 of 1692
REJ09B0393-0100