SH7280 Datasheet, PDF (100/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 3 MCU Operating Modes
H'0000 0000
Modes 0 and 1
On-chip ROM disabled mode
CS0 space
H'03FF FFFF
H'0400 0000
H'07FF FFFF
H'0800 0000
H'0BFF FFFF
H'0C00 0000
H'0FFF FFFF
H'1000 0000
H'13FF FFFF
H'1400 0000
H'17FF FFFF
H'1800 0000
H'1BFF FFFF
H'1C00 0000
H'1FFF FFFF
H'2000 0000
CS1 space
CS2 space
CS3 space
CS4 space
CS5 space
CS6 space
CS7 space
Mode 2
On-chip ROM enabled mode
H'0000 0000
H'0003 FFFF
H'0004 0000
H'01FF FFFF
H'0200 0000
H'03FF FFFF
H'0400 0000
H'07FF FFFF
H'0800 0000
H'0BFF FFFF
H'0C00 0000
H'0FFF FFFF
H'1000 0000
H'13FF FFFF
H'1400 0000
H'17FF FFFF
H'1800 0000
H'1BFF FFFF
H'1C00 0000
H1FFF FFFF
H'2000 0000
On-chip ROM (256 Kbytes)
Reserved area
CS0 space
CS1 space
CS2 space
CS3 space
CS4 space
CS5 space
CS6 space
CS7 space
H'0000 0000
H'0003 FFFF
H'0004 0000
Mode 3
Single chip mode
On-chip ROM (256 Kbytes)
Reserved area
Reserved area
Reserved area
H'FFF7 FFFF
H'FFF8 0000
H'FFF8 2FFF
H'FFF8 3000
H'FFFB FFFF
H'FFFC 0000
H'FFFC FFFF
H'FFFD 0000
On-chip RAM (12 Kbytes)
Reserved area
SDRAM mode setting space
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
H'FFF7 FFFF
H'FFF8 0000
H'FFF8 2FFF
H'FFF8 3000
H'FFFB FFFF
H'FFFC 0000
H'FFFC FFFF
H'FFFD 0000
On-chip RAM (12 Kbytes)
Reserved area
SDRAM mode setting space
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
H'FFF7 FFFF
H'FFF8 0000
H'FFF8 2FFF
H'FFF8 3000
On-chip RAM (12 Kbytes)
Reserved area
H'FFFD FFFF
H'FFFE 0000
H'FFFF FFFF
On-chip peripheral
I/O registers
Figure 3.6 SH7243F (256 KB) Address Map for Each Operating Mode
Rev. 1.00 Jun. 26, 2008 Page 70 of 1692
REJ09B0393-0100