SH7280 Datasheet, PDF (458/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 10 Direct Memory Access Controller (DMAC)
CK
Bus cycle
DREQ
(Rising)
DACK
(Active-high)
CPU
CPU
DMAC
Burst acceptance
Non sensitive period
DMAC
Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection
CK
Bus cycle
DREQ
(Overrun 0 at
high level)
DACK
(Active-high)
CPU
CPU
DMAC
1st acceptance
Non sensitive period
2nd
acceptance
Acceptance
start
CK
Bus cycle
DREQ
(Overrun 1 at
high level)
DACK
(Active-high)
CPU
CPU
1st acceptance
Non sensitive period
DMAC
2nd acceptance
DMAC
3rd
acceptance
Acceptance
start
Acceptance
start
Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection
Rev. 1.00 Jun. 26, 2008 Page 428 of 1692
REJ09B0393-0100