SH7280 Datasheet, PDF (1014/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
20.3.5 A/D Bypass Control Registers 0 to 2 (ADBYPSCR_0 to ADBYPSCR_2)
For A/D conversion of group A (GrA), it can be selected whether to use the sample-and-hold
circuits dedicated to the group A channels or to use the impedance-conversion circuits in the same
way as A/D conversion of other channels.
Setting the SH bit in ADBYPSCR_0 to 0 selects the impedance-conversion circuits; setting the SH
bit to 1 selects the sample-and-hold circuits dedicated to the channels. When the impedance-
conversion circuit is selected, the A/D conversion time does not include the time for sampling in
the dedicated sample-and-hold circuits. For details, refer to section 20.4, Operation.
Setting the OFC bit to 0 enables the offset canceling processing (OFC) for the comparator in the
A/D converter; setting the OFC bit to 1 disables automatic correction during A/D conversion. To
obtain a higher accuracy, clear the OFC bit to 0.
The function of the SH bit in this register is available only for A/D converter_0. A/D converter_1,
2 are always in the same state as when the SH bit is set to 0.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
OFC SH
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W
Initial
Bit Bit Name Value R/W
7 to 2 
All 0
R
1
OFC
0
R/W
0
SH
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Offset Canceling Bypass
0: A/D conversion in high-accuracy automatic correction
mode
1: A/D conversion without no correction
Dedicated Sample-and-Hold Circuit Select
(ADBYPSCR_0 only)
0: Selects the impedance-conversion circuits
1: Selects the sample-and-hold circuits
This bit is a reserved bit in ADBYPSCR_1 and
ADBYPSCR_2 registers. The writing value should always
be 0.
Rev. 1.00 Jun. 26, 2008 Page 984 of 1692
REJ09B0393-0100