SH7280 Datasheet, PDF (921/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
18.3.5 SS Status Register (SSSR)
SSSR is a status flag register for interrupts.
Bit: 7
6
5
- ORER -
Initial value: 0
0
0
R/W: R R/W R
4
3
2
1
0
- TEND TDRE RDRF CE
0
0
1
0
0
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7

0
R
6
ORER
0
R/W
5, 4 
All 0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Overrun Error
If the next data is received while RDRF = 1 in data
transfer mode (TE=RE=1), an overrun error occurs,
indicating abnormal termination. SSRDR stores 1-frame
receive data before an overrun error occurs and loses
data to be received later. While ORER = 1, consecutive
serial reception cannot be continued. Serial
transmission cannot be continued, either.
[Setting condition]
• When one byte of the next serial reception is
completed with RDRF = 1 in data transfer mode
(TE=RE=1).
[Clearing condition]
• When writing 0 after reading ORER = 1
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Jun. 26, 2008 Page 891 of 1692
REJ09B0393-0100