SH7280 Datasheet, PDF (1448/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 26 Flash Memory
(1) SCI Interface Setting by Host
When boot mode is initiated, this LSI measures the low period of asynchronous SCI-
communication data (H'00), which is transmitted consecutively by the host. The SCI
transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate
of transmission by the host by means of the measured low period and transmits the bit adjustment
end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment end sign
(H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When reception is not
executed normally, boot mode is initiated again (reset) and the operation described above must be
executed. The bit rate between the host and this LSI is not matched because of the bit rate of
transmission by the host and system clock frequency of this LSI. To operate the SCI normally, the
transfer bit rate of the host must be set to 9,600 bps or 19,200 bps.
The system clock frequency which can automatically adjust the transfer bit rate of the host and the
bit rate of this LSI is shown in table 26.7. Boot mode must be initiated in the range of this system
clock.
Start _{D0 D1 D2 D3 D4 D5 D6}
bit
D7 ^{Stop bit}
Measure low period (9 bits) (data is H'00)
High period of
at least 1 bit
Figure 26.7 Automatic Adjustment Operation of SCI Bit Rate
Table 26.7 Peripheral Clock (Pφ) Frequency that Can Automatically Adjust Bit Rate of
This LSI
Host Bit Rate
9,600 bps
19,200 bps
Peripheral Clock (Pφ) Frequency That Can Automatically Adjust
LSI's Bit Rate
20 to 25 MHz
Rev. 1.00 Jun. 26, 2008 Page 1418 of 1692
REJ09B0393-0100